Lead frame, semiconductor device, and lead frame manufacturing method

ABSTRACT

A lead frame includes: a lead portion; a plating layer that is provided on a connected area of the lead portion, the connected area being an area connected with a semiconductor element; a recessed portion that is provided around the plating layer on the lead portion; and an oxidized layer that is provided on a surface including the recessed portion of the lead portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2018-209997, filed on Nov. 7,2018, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to a lead frame, asemiconductor device, and a lead frame manufacturing method.

BACKGROUND

As a thin profile semiconductor device, a flip chip (FC)-quad flatnon-leaded package (QFN)-type semiconductor device has been known. Suchan FC-QFN semiconductor device includes a semiconductor element that isplaced on a stage of the lead frame and is encapsulated with a moldresin, and lead portions that are partly exposed from the rear surfaceof the mold resin covering the opposite side of the stage.

In the fabrication process of such an FC-QFN semiconductor device, tobegin with, a metal substrate is etched to achieve a lead frame that hasa matrix-like arrangement of areas corresponding to semiconductorelements. In the lead frame, the areas corresponding to thesemiconductor elements are partitioned by connecting bars. Theconnecting bars are also referred to as sawing bars. A plurality of leadportions provided in a manner surrounding each of the semiconductorelements are connected to the connecting bars.

In the FC-QFN semiconductor device fabrication process, Cu pillars arethen placed on a semiconductor element, and solder is applied to thetips of the Cu pillars. The semiconductor element with the Cu pillarshaving solder applied to their tips is then reversed and placed on thelead frame, and the semiconductor element is bonded to the lead frame bymelting the solder. Molding for encapsulating the semiconductor elementwith a mold resin is then carried out. Sawing for separating thesemiconductor elements by cutting the mold resin and the connecting barswith a sawing blade is then performed.

In the FC-QFN semiconductor device fabrication process, after thesemiconductor element is reversed and placed on the lead frame, reflowis carried out to bond the semiconductor element to the lead frame. Ifthe lead frame surface is made of Cu, it is quite possible that thesolder does not wet-spread across the lead frame, so that thesemiconductor element is caused to move, and the position thereof doesnot stabilize. To address this issue, having been available to improvethe bondability and to prevent the misalignment of the chip is atechnology for providing Ag plating with which solder exhibits highwettability to the bonding surface, and treating the area surroundingAg-plated area with copper oxide that is not wettable with the solder.Related Art examples are disclosed in Japanese Laid-open PatentPublication No. 2004-349497 and Japanese Laid-open Patent PublicationNo. 2004-332105.

However, because the process for forming the plating layer on a part ofthe bonding surface is carried out after the shape of the lead frame isformed by etching, for example, the positions of the area of the platinglayer and the terminals may become misaligned with respect to eachother. Furthermore, when the plating layer is positioned near an endsurface of the lead frame, the plating may be chipped due to such amisalignment.

SUMMARY

According to an aspect of an embodiment, a lead frame includes: a leadportion; a plating layer that is provided on a connected area of thelead portion, the connected area being an area connected with asemiconductor element; a recessed portion that is provided around theplating layer on the lead portion; and an oxidized layer that isprovided on a surface including the recessed portion of the leadportion.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic plan view of a lead frame;

FIG. 2 is a plan view of a unit lead frame;

FIG. 3 is a schematic giving an enlarged view of an inner end of thelead;

FIG. 4 is a sectional view of the lead frame across the line IV-IV inFIG. 2;

FIG. 5 is a sectional view of the lead frame across the line V-V in FIG.3;

FIG. 6 is a sectional view of a semiconductor device fabricated usingthe lead frame according to the embodiment;

FIG. 7 is an enlarged view of the part where the semiconductor elementin the semiconductor device is bonded to the lead;

FIG. 8A is a sectional view illustrating a lead frame manufacturingmethod according to the embodiment;

FIG. 8B is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8C is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8D is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8E is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8F is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8G is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8H is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8I is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8J is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8K is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 8L is a sectional view illustrating the lead frame manufacturingmethod according to the embodiment;

FIG. 9 is a schematic for explaining removal of plating resist;

FIG. 10 is an enlarged sectional view of a part around a plating layeron the lead on which a plating resist layer is formed;

FIG. 11 is an enlarged sectional view of the part around the platinglayer on the lead frame after the plating resist is removed;

FIG. 12A is a sectional view illustrating a method for fabricating thesemiconductor device according to the embodiment;

FIG. 12B is a sectional view illustrating the method for fabricating thesemiconductor device according to the embodiment;

FIG. 12C is a sectional view illustrating the method for fabricating thesemiconductor device according to the embodiment;

FIG. 13 is a schematic illustrating the bonding between a Cu pillarhaving a circular bonding surface and a rectangular plating layer;

FIG. 14A is a schematic illustrating one example of the plating layerreaching the outer edges of the lead in the width direction; and

FIG. 14B is a schematic illustrating one example of the plating layerreaching the outer edges of the lead in the width direction.

DESCRIPTION OF EMBODIMENT

An embodiment of a lead frame, a semiconductor device, and a lead framemanufacturing method disclosed herein will now be explained in detailwith reference to some drawings. The embodiment described below is notintended to limit the scope of the lead frame, the semiconductor device,and the lead frame manufacturing method disclosed herein in any way.

Configuration of Lead Frame

FIG. 1 is a schematic plan view of a lead frame. As illustrated in FIG.1, this lead frame 1 includes a substrate frame 2 having a substantiallyrectangular shape in a plan view. As a material for the substrate frame2, Copper (Cu), a Cu-based alloy, iron-nickel (Fe—Ni), or an Fe—Ni-basedalloy, for example, may be used. The thickness of the substrate frame 2may be set to 0.05 millimeter to 0.25 millimeter or so, for example.

In the substrate frame 2, a plurality of resin-molded areas 3 aredefined in a manner separated from one another. In this embodiment, thesubstrate frame 2 has three resin-molded areas 3. In each of theresin-molded areas 3, a plurality of unit lead frames 100 are formed ina connected fashion, in a matrix-like shape. In this embodiment, each ofthe resin-molded areas 3 includes an arrangement of five-by-five unitlead frames 100. On each of these unit lead frames 100, a semiconductorelement is placed, and each of the unit lead frames 100 is eventuallycut out as an independent semiconductor device (package). Around theperimeter of each of the resin-molded areas 3, a rail portion 4extending in a longitudinal direction (the left-and-right direction inFIG. 1), and a rail portion 5 extending in a width direction (theup-and-down direction in FIG. 1) are provided. In the process ofsemiconductor device assembly, a semiconductor element is placed on eachof the unit lead frames 100, and the semiconductor elements are moldedat once, in units of one resin-molded area 3.

FIG. 2 is a plan view of a unit lead frame 100. In the explanationhereunder, the unit lead frame 100 will be simply referred to as a leadframe 100. In the explanation hereunder, a “front surface” refers to asurface facing the stage on which a semiconductor element 21, which willbe described later, is to be placed, and a “rear surface” refers to thesurface facing the opposite side of the stage on which the semiconductorelement 21 is to be placed.

The lead frame 100 includes a frame portion 101 and a plurality of leads102 supported by the frame portion 101. The frame portion 101 has arectangular frame-like shape. The leads 102 are provided in a mannerperpendicularly intersecting with the frame portion 101, and extendinginwards from the frame portion 101. The leads 102 are cut off across thecutting line L1, and come to serve as members of the semiconductordevice.

On an inner end of the lead 102, a plating layer 23 is provided. FIG. 3is a schematic giving an enlarged view of the inner end of the lead. Theplating layer 23 is provided to facilitate implementation of asemiconductor element 21 on the lead 102. For the plating layer 23,silver (Ag) plating may be used, for example. For the plating layer 23,a nickel (Ni) plating, palladium (Pd) plating, gold (Au) plating, or thelike may also be used. Furthermore, the plating layer 23 may consist ofa plurality of plating layers, e.g., a Ni plating layer and an Agplating layer formed on top of each other. The Ni plating layer and theAu plating layer may be placed on top of each other, for example, in theorder listed herein, from the side of the lead 102, as the plating layer23. It is also possible to place a Ni plating layer, a Pd plating layer,and an Au plating layer on top of one another, in the order listedherein, from the side of the lead 102, as the plating layer 23. Arecessed portion 24 is then formed in a manner surrounding the platinglayer 23.

FIG. 4 is a sectional view of the lead frame across the line IV-IV inFIG. 2. As illustrated in FIG. 4, the lead 102 has a base plate 26 thatis a metal plate. The base plate 26 is conductive. As the material forthe base plate 26, a metal such as copper (Cu), a Cu alloy, or a 42alloy that is an alloy of iron and nickel may be used, for example.

The base plate 26 has a smaller thickness near the center in alongitudinal direction extending from the frame portion 101 toward thecenter, as illustrated in FIG. 2, the thickness being smaller by beingrecessed from the side of the rear surface. In this embodiment, a partof the rear surface of the base plate 26 is recessed, but withoutlimitation thereto, and it is also possible not to remove any of therear surface of the base plate 26, or to remove the thickness from theentire rear surface, for example.

The lead 102 has the plating layer 23 that is provided to an area nearthe tip of the base plate 26 in a direction travelling toward the centerof the lead frame 100 illustrated in FIG. 2. The lead 102 also has therecessed portion 24 that is recessed from the front surface of the baseplate 26, in a manner surrounding the plating layer 23. The lead 102also has an oxidized layer 25 in the area other than the area of theplating layer 23 in the front surface. The oxidized layer 25 is alsoprovided to the area corresponding to the recessed portion 24. Theoxidized layer 25 is a film of oxidized copper, for example.

FIG. 5 is a sectional view of the lead frame across the line V-V in FIG.3. In this embodiment, the area of the plating layer 23 is circular, andthe recessed portion 24 has an annular shape surrounding the platinglayer 23. Therefore, the cross section illustrated in FIG. 5 across theline V-V is the same as an enlargement of FIG. 4 near the plating layer23. As illustrated in FIG. 5, the cross section of the recessed portion24 delineates a semi-circular curve. The oxidized layer 25 is thenprovided to the area including the entire area of the recessed portion24 provided in a manner surrounding the plating layer 23.

Structure of Semiconductor Device

A semiconductor device 200 fabricated using the lead frame 100 accordingto the embodiment will now be explained with reference to FIG. 6. FIG. 6is a sectional view of the semiconductor device fabricated using thelead frame according to the embodiment. FIG. 6 illustrates a crosssection of the semiconductor device 200 at the same position as thecross section across the line IV-IV in FIG. 2, but with a semiconductorelement 21 mounted on the lead 102.

Examples of the semiconductor element 21 include an integrated circuit,a large-scale integrated circuit, a transistor, a thyristor, and adiode. The semiconductor element 21 has Cu pillars 22 serving aselectrodes. The Cu pillars 22 have the same shape, in the plan view, asthe plating layer 23, for example. The Cu pillar 22 is then connected tothe plating layer 23 on the lead 102 via solder 30. As the solder 30, asolder ball may be used, for example.

As illustrated in FIG. 7, the oxidized layer 25 is formed in a mannersurrounding the plating layer 23. FIG. 7 is an enlarged view of the partwhere the semiconductor element in the semiconductor device is bonded tothe lead. The wettability of the solder 30 with the oxidized layer 25 isnot high. Therefore, by covering the area around the plating layer 23with the oxidized layer 25, the solder 30 is suppressed from spreadingto an extent larger than necessary (bleeding out), on the lead 102.

Referring back to FIG. 6, the explanation is continued. Thesemiconductor elements 21 and the leads 102 are covered by mold resin27. As the mold resin 27, an epoxy resin or a silicone resin may beused, for example. In each of the leads 102, an outer terminal 28 isexposed from the mold resin 27, on the rear surface of the semiconductordevice 200. In each of the leads 102, the outer terminal 28 is coveredby a plating layer 29.

Lead Frame Manufacturing Method

A method for manufacturing the lead frame 100 illustrated in FIG. 2 willnow be explained with reference to FIGS. 8A to 8L. FIGS. 8A to 8L aresectional views illustrating the lead frame manufacturing methodaccording to the embodiment.

To begin with, as illustrated in FIG. 8A, a flat plate-like metalsubstrate 41 is prepared. A metal such as copper, a copper alloy, or aFe—Ni alloy may be used, as the material for the metal substrate 41.

At the next step, as illustrated in FIG. 8B, a photoresist 42 a and aphotoresist 43 a are provided across the entire front and rear surfacesof the metal substrate 41, respectively. For example, the photoresists42 a and 43 a are achieved by pasting a film-like resist, which iscalled a dry film resist, on the metal substrate 41. Alternatively, itis also possible to form the photoresists 42 a and 43 a by applyingliquid resist solution and finishing the solution, instead of using thedry film resist.

At the next step, as illustrated in FIG. 8C, the photoresists 42 a, 43 aare exposed using photomasks 44 and 45 having a predetermined pattern.

At the next step, as illustrated in FIG. 8D, the exposed photoresists 42a and 43 a are developed into resist layers 42 and 43 havingpredetermined openings.

Specifically, an opening 42 b is formed in the area that is to bethrough-etched, on the front surface of the metal substrate 41.Furthermore, an opening 42 c is formed in the area that is to behalf-etched, and that is the area where the recessed portion 24 is to beformed, on the front surface of the metal substrate 41. On the rearsurface of the metal substrate 41, an opening 43 b is formed across thearea to be through-etched and the area to be half-etched.

At the next step, as illustrated in FIG. 8E, the base plate 26 iscreated by etching the metal substrate 41 with an etching solution,using the resist layers 42 and 43 as a mask (anti-corrosion mask). Theetching solution can be chosen as appropriate, depending on the materialused for the metal substrate 41. For example, when copper is used as themetal substrate 41, ferric chloride solution or cupric chloride solutionis used, for example. The metal substrate 41 is etched by spraying theetching solution onto the front surface and the rear surface of themetal substrate 41, using a spray, for example. As a result, the baseplate 26 having a plurality of leads 102 is formed. As the leads 102 areformed, the recessed portions 24 recessed from the front surface of thebase plate 26 are also formed. At this time, because the size of theopening 42 c is small, a smaller amount of etching solution is suppliedto the opening 42 c, compared to that supplied to the opening 42 b.Therefore, the recessed portion 24 is formed by half-etching to such adegree that the recessed portion 24 does not penetrate through to therear surface of the base plate 26. These recessed portions 24 are formedat the same time as the leads 102 are formed, therefore, do not becomemisaligned with respect to the leads 102, and can be formed at desiredpositions.

At the next step, as illustrated in FIG. 8F, the resist layers 42, 43are peeled off and removed.

At the next step, as illustrated in FIG. 8G, the lead frame 100 in thecondition as illustrated in FIG. 8F is soaked into liquid resist, aplating resist 64 a is applied to the area including the recessedportion 24, and the lead frame 100 is then dried. The plating resist 64a is a negative resist so that exposed parts remain.

At the next step, as illustrated in FIG. 8H, the plating resist 46 a isexposed, using a photomask 47 covering the area surrounded by therecessed portion 24.

At the next step, as illustrated in FIG. 8I, a plating resist layer 46with an opening 46 b via which the area surrounded by the recessedportion 24 is exposed is then formed by developing the exposed platingresist 46 a.

At the next step, as illustrated in FIG. 8J, the plating layer 23 isformed on the exposed part of the front surface of the base plate 26,being exposed via the opening 46 b. The plating layer 23 is formed byelectroplating, by receiving power supply via the base plate 26, forexample. It is also possible to use electrodeless plating, instead ofelectroplating, to form the plating layer 23.

The plating resist layer 46 is then peeled off and removed, asillustrated in FIG. 8K.

At the next step, as illustrated in FIG. 8L, the oxidized layer 25 isthen formed on the front surface of the base plate 26. The oxidizedlayer 25 can be achieved by oxidizing the front surface of the baseplate 26. This oxidation is an oxidation not reacting with the platinglayer 23. For example, as the oxidation, it is possible to use forcedoxidation in which the lead frame 100 is immersed in a blackeningsolution and anodized. In such a case, it is possible to suppress theoxidation of the rear surface of the lead frame 100 while the frontsurface is oxidized, by setting the side of the front surface as ananode, and the side of the rear surface as a cathode. Furthermore, thisoxidation may also be achieved by spraying a blackening solution ontothe lead frame 100. Alternatively, it is also possible to use a methodsuch as pasting a film onto the part that is not to be oxidized so thata predetermined area is oxidized, for example. In this oxidation, onlythe front surface of the base plate 26 may be oxidized, or the front andside surfaces of the base plate 26 may be oxidized. The oxidized layer25 formed by the anodization contains copper I oxide (Cu₂O), copper IIoxide (CuO) or copper hydroxide (Cu(OH)₂), for example.

The blackening solution is a mixture of a strong alkaline compound andan oxidant, for example. Sodium hydroxide or potassium hydroxide may beused as the strong alkaline compound, for example, and the compound maybe solely used, or two or more of these compounds may be used as amixture. As the oxidant, sodium chlorite may be used, for example. Anadditive may also be added thereto. As an example of the blackeningsolution, it is possible to use a solution containing 0 g/L to 100 g/Lof sodium chlorite (NaClO₂), 5 g/L to 60 g/L of sodium hydroxide (NaOH),and 0 g/L to 200 g/L of trisodium phosphate (Na₃PO₄). The oxidation maybe carried out under conditions including a solution temperature of 50degrees to 80 degrees, oxidation time of approximately 1 second to 20seconds, and a cathode current density of 0.2 A/cm² to 10 A/cm², forexample.

In this manner, the lead frame 100 having the leads 102 is manufactured.

Removal of the plating resist from the area surrounded by the recessedportion 24 will now be explained in detail with reference to FIG. 9.FIG. 9 is a schematic for explaining removal of the plating resist.

A condition 61 represents a condition after the plating resist 46 a hasbeen formed on the front surface of the base plate 26. The condition 61represents a condition illustrated in FIG. 8G. As illustrated as acondition 62, the photomask 47 made of a film or glass, and covering thearea surrounded by the recessed portion 24 is then placed. Thiscondition represents the condition illustrated in FIG. 8H.

The photomask 47 has a size smaller than the area inside of the outercircumference of the recessed portion 24, but larger than the areainside of the inner circumference of the recessed portion 24.Specifically, it is preferable for the photomask 47 to have a widthallowance twice or more the misalignment capability of the device forplacing the photomask 47, in any directions with respect to the area onwhich the plating layer 23 is intended to be formed. For example,assuming that the device for placing the photomask 47 produces amisalignment of 50 micrometers at the maximum, it is preferable, in thisembodiment, for the photomask 47 to have a diameter larger than thediameter of the circular area inside of the inner circumference of therecessed portion 24, by a distance of 100 micrometers. In other words,when the centers of the photomask 47 and of the circular area surroundedby the inner circumference of the recessed portion 24 match, thephotomask 47 sticks out from the inner circumference of the recessedportion 24 by 50 micrometers.

Furthermore, it is also preferable, in relation to the size of therecessed portion 24, for the distance from the inner circumference tothe outer circumference thereof to be twice or more the misalignmentcapability of the device for placing the photomask 47. In other words,the photomask 47 may occupy an area up to a half the distance betweenthe outer circumference and the inner circumference of the recessedportion 24. Furthermore, it is more preferable if the recessed portion24 is deeper, provided that the depth of the recessed portion 24 isdetermined by the plate thickness of the base plate 26, and takes up 50%or so of the plate thickness.

A condition 62 is the condition after being exposed, by being irradiatedwith light, with the photomask 47 covering the area inside of the innercircumference of the recessed portion 24. In FIG. 9, the irradiatinglight that leads to the condition 62 is indicated by arrows. At thistime, the light having entered between the photomask 47 and the outercircumference of the recessed portion 24 is diffracted, refracted, andis reflected on the surface of the recessed portion 24. As a result, thearea not directly irradiated with the light, between the photomask 47and the inner circumference of the recessed portion 24, is also exposed.As a result, as indicated as a condition 63, it is possible to exposealmost the entire area other than the area surrounded by the innercircumference of the recessed portion 24 and with which the photomask 47has been in contact, so that the plating resist 46 a can be mainlyremoved from the area surrounded by the inner circumference of therecessed portion 24 and with which the photomask 47 has been in contact.In this manner, the plating resist layer 46 having the opening 46 b,through which the area surrounded by the inner circumference of therecessed portion 24 is exposed, is formed, as indicated as the condition63. This condition represents the condition illustrated in FIG. 8I.

Then, by forming the plating layer 23 on the lead 102 in the condition63, the plating layer 23 can be formed at the position of the opening 46b of the plating resist layer 46, as illustrated in FIG. 10. In thismanner, the plating layer 23 can be formed at the desired position ofthe lead 102. FIG. 10 is an enlarged sectional view of a part around theplating layer 23 on the lead frame on which the plating resist layer 46is formed. This condition represents the condition illustrated in FIG.8J.

Then, by removing the plating resist layer 46 from the lead 102 in thecondition illustrated in FIG. 10, it is possible to obtain the lead 102with the plating layer 23 formed at a desired position of the lead 102,as illustrated in FIG. 11. FIG. 11 is an enlarged sectional view of thepart around the plating layer 23 on the lead frame after the platingresist layer 46 is removed. This condition represents the conditionillustrated in FIG. 8K.

Method for Fabricating Semiconductor Device

A method for fabricating the semiconductor device 200 illustrated inFIG. 6 will now be explained with reference to FIGS. 12A to 12C. FIGS.12A to 12C are sectional views illustrating a method for fabricating thesemiconductor device according to the embodiment.

At the step illustrated in FIG. 12A, the semiconductor element 21 isimplemented on the lead 102. The solder 30 is attached to at least oneof the plating layers 23 on the lead frame 100 and the Cu pillars 22that are the electrodes of the semiconductor element 21. The solder 30may be attached using solder balls. The semiconductor element 21 is thenreversed so that the Cu pillars 22 face downwards. The plating layers 23are then aligned with the Cu pillars 22, and the semiconductor element21 is connected to the lead 102 by allowing the solder 30 having moltenduring the reflow process to solidify. This process is referred to as aflip-chip bonding.

At this time, in the lead frame 100 according to the embodiment, theplating layer 23 is formed in the area surrounded by the innercircumference of the recessed portion 24, where the plating layer 23 isless likely to be misaligned with respect to the lead 102. Therefore,when the plating layer 23 is coupled to the Cu pillar 22, both can beensured to have a sufficient coupling surface, so that the semiconductorelement 21 and the lead 102 can be bonded reliably.

At the step illustrated in FIG. 12B, the mold resin 27 is formed in amanner covering a part of the lead 102, and the semiconductor element21. The mold resin 27 is formed using a method such as transfer molding,compression molding, or injection molding. In this condition, the outerterminals 28 of the leads 102 are exposed from the mold resin 27.

At the step illustrated in FIG. 12C, the plating layer 29 is formed onthe outer terminal 28 of the lead 102, where the outer terminal 28 isexposed from the mold resin 27. This plating layer 29 is tin plating orsolder plating, for example. The plating layer 29 is made viaelectroplating or electrodeless plating, for example. The semiconductordevice 200 illustrated in FIG. 6 is then acquired by dicing the leadframe 100 along the cutting line L1 in a dicing process.

As explained above, in the lead frame according to the embodiment, aplating resist is applied to a substrate having a recessed portion in amanner surrounding a desired area on which the plating layer is intendedto be formed, and the substrate is exposed, with desired area covered bya mask having a size larger than the desired area, so that the platingresist is removed from the desired area and the plating layer is formedin the desired area. In this manner, the plating layer can be formed ata desired position. In particular, by providing the recessed portion ina manner surrounding the desired area to be plated, plating can beapplied reliably to the desired area.

Furthermore, by disposing the oxidized layer in a manner surrounding theplating layer, the wet solder for coupling the plating layer and theelectrodes can be suppressed from spreading any further. In this manner,it is possible to suppress misalignment, in coupling the electrodes ofthe semiconductor element to the leads, so that the semiconductorelement can be bonded reliably to the leads.

Furthermore, by making the bottom surface of the recessed portion acurved surface, even if a mask having a size larger than the desiredarea is placed, considering the misalignment precision of the machine,even the part behind the mask can be exposed by reflection, so that theoxidized layer can be formed reliably to the part other than the desiredarea.

Furthermore, in this embodiment, silver plating is applied, for example,to the desired area of the lead made of copper. In this manner, wetsolder is allowed to spread across the desired area, so that electroniccomponents such as an IC chip can be bonded reliably to the lead.

MODIFICATIONS

The embodiment described above may also be implemented in theconfigurations described below. In the explanation hereunder, themembers that are the same as those in the embodiment are assigned withthe same reference numerals, and explanations thereof will be sometimespartly or entirely omitted.

In the example explained in the embodiment described above, it isassumed that the shape of the surface to which the Cu pillar 22 issoldered is circular, but the Cu pillar 22 may have another shape. Forexample, the Cu pillar 22 may have an elliptic or rectangular shape. Insuch a case, it is preferable for the plating layer 23 to have the sameshape as the Cu pillar 22.

Furthermore, when it is acceptable for the solder 30 to flow by someextent, the plating layer 23 may be larger than the Cu pillar 22 to theextent to which the flowing of the solder 30 is acceptable.

Furthermore, the Cu pillar 22 and the plating layer 23 may havedifferent shapes, as long as the Cu pillar 22 has a size included in theplating layer 23, and the size difference is within the range in whichflowing of the solder 30 is acceptable. For example, as illustrated inFIG. 13, when the Cu pillar 22 has a circular bonding surface, theplating layer 23 may have a rectangular shape in a size including thecircular shape. FIG. 13 is a schematic illustrating a relation between aCu pillar having a circular bonding surface, and a rectangular platinglayer.

Furthermore, in the example explained in the embodiment described above,it is assumed that the plating layer 23 has a size included in the frontsurface of the lead 102, but the plating layer 23 may reach the outeredges of the lead 102, in a width direction of the lead 102 in FIG. 2,that is, in a direction perpendicularly intersecting with the directiontravelling from the frame portion 101 to the center. For example, asillustrated in FIG. 14A, the plating layer 23 extends to both sides ofthe lead 102 in the width direction. In such a configuration, therecessed portion 24 is laid in a manner penetrating the lead 102 in thewidth direction. Furthermore, as illustrated in FIG. 14B, the recessedportion 24 may be linear, and the plating layer 23 may have arectangular shape reaching both sides of the lead 102 in the widthdirection. FIGS. 14A and 14B are schematic illustrating some examples ofthe plating layer reaching the outer edges of the lead in the widthdirection.

As explained above, even when the shape of the bonding surface betweenthe plating layer and the electrode of the semiconductor element is notcircular, or when the plating layer reaches the outer edges of the lead,it is possible to form the plating layer at a desired position byproviding a recessed portion. Furthermore, by disposing the oxidizedlayer in a manner surrounding the plating layer, the wet solder forcoupling the plating layer and the electrode of the semiconductorelement can be suppressed from spreading any further. In this manner, itis possible to suppress misalignment, in coupling the electrodes of thesemiconductor element to the leads, so that the semiconductor elementcan be bonded reliably to the leads.

Furthermore, even when the plating layer has a shape different from thatof the bonding surface of the electrode of the semiconductor element,the electrode can be bonded reliably to the lead, as long as the amountof flow of the solder is within an acceptable range.

According to one aspect of the present invention, it is possible tosuppress chipping of the plating layer.

All examples and conditional language recited herein are intended forpedagogical purposes of aiding the reader in understanding the inventionand the concepts contributed by the inventor to further the art, and arenot to be construed as limitations to such specifically recited examplesand conditions, nor does the organization of such examples in thespecification relate to a showing of the superiority and inferiority ofthe invention. Although the embodiments of the present invention havebeen described in detail, it should be understood that the variouschanges, substitutions, and alterations could be made hereto withoutdeparting from the spirit and scope of the invention.

What is claimed is:
 1. A lead frame comprising: a lead portion; aplating layer that is provided on a connected area of the lead portion,the connected area being an area connected with a semiconductor element;a recessed portion that is provided around the plating layer on the leadportion; and an oxidized layer that is provided on a surface includingthe recessed portion of the lead portion.
 2. The lead frame according toclaim 1, wherein a bottom surface of the recessed portion is a curvedsurface.
 3. The lead frame according to claim 1, wherein the recessedportion surrounds an entire perimeter of the plating layer.
 4. The leadframe according to claim 1, wherein the lead portion is made of copper,and the plating layer is made of silver.
 5. The lead frame according toclaim 1, wherein the oxidized layer is made of oxide of a metal of whichthe lead portion is made.
 6. The lead frame according to claim 1,wherein the oxidized layer covers an upper surface and a side surface ofthe lead portion, and exposes a lower surface of the lead portion. 7.The lead frame according to claim 1, wherein the oxidized layer containshydroxide.
 8. A semiconductor device comprising: a lead portion; aplating layer that is provided on a connected area of the lead portion,the connected area being an area connected with a semiconductor element;a recessed portion that is provided around the plating layer on the leadportion; an oxidized layer that is provided on a surface including therecessed portion of the lead portion; a semiconductor element that has aterminal connected to the plating layer via solder; and an encapsulationresin that covers the lead portion and the semiconductor element.
 9. Alead frame manufacturing method comprising: first forming a lead and arecessed portion that is provided around a connected area beingconnected with a semiconductor element on the lead; second forming aplating layer on the connected area; and third forming an oxidized layeron a surface including the recessed portion of the lead.
 10. The leadframe manufacturing method according to claim 9, wherein the firstforming includes: forming an etching resist layer on a metal substrate;forming the lead having the recessed portion in an area adjacent to apredetermined area of the metal substrate by half-etching the metalsubstrate, using the etching resist layer as a mask; and removing theetching resist layer from the metal substrate, the second formingincludes: forming a plating resist layer to an area including therecessed portion and the predetermined area of the lead; removingplating resist from the predetermined area, by exposing and developingthe plating resist layer with the predetermined area covered by a maskhaving an area larger than the predetermined area; and forming a platinglayer in the predetermined area, and the third forming includes:removing the plating resist layer from the lead; and forming an oxidizedlayer in an area including the recessed portion and excluding thepredetermined area of the lead.
 11. The lead frame manufacturing methodaccording to claim 9, wherein the third forming includes forming theoxidized layer by oxidizing a metal serving as a base plate of the lead.